The design and architecture of very large scale integrated (VLSI) circuits such as processors are quite complicated. It is generally recognized that performance is often sacrificed in order to ensure reliable operation of the processor. With the development of multi-core processors, the ability to reliably deliver data becomes a bigger concern.
The development of multi-core processors leads to additional connections and structural complexity. Links between cores may lengthen and the propagation time for voltage levels typically increases. In addition, the proliferation of components in multi-core processors, the smaller size and increased density of transistors makes it likely, for example, that on-chip switches and links will fail either intermittently or permanently. As a result, the ability to deliver data in the on-chip network of the multi-core processor becomes less reliable.
At the same time, there are many applications where reliable communication is a requirement. Parallelized applications, which are distributed to and performed by multiple cores, often rely on the tasks being performed by those cores to finish before moving forward. When communication fails in the on-chip network, the system or application may hang or otherwise fail.
The ability to reliably communicate between cores is an important concern in multi-core processor design. As previously stated, however, the development of a highly reliable processor likely sacrifices performance and likely increases cost. In order to improve performance, applications operating on multi-core processors face the prospect of achieving reliable communication on a relatively unreliable on-chip network.